Write-inhibit circuit, semiconductor integrated circuit using the same, ink cartridge including the semiconductor integrated circuit, and ink-jet recording apparatus

ABSTRACT

Chip area and operating current is reduced in a chip having a write-inhibit circuit that uses a data-writing request signal WR and a write-control signal WRITE to inhibit data writing. By comparing a reference current Iref and a drive current ID, a current-mirror circuit CM can monitor the voltage of a power supply VDD. When the voltage of the power supply VDD is sufficiently high, the data-writing request signal WR is unchanged. Conversely, when the voltage of the power supply VDD is not sufficiently high, a transistor T6 producing reference-current I D  and a buffer B2 cause the write-control signal to be low “L” irrespective of whether the data-writing request signal WR is at “H” or at “L”. Thus, miswriting can be prevented when the power-supply voltage decreases, since writing by the data-writing request signal WR is impossible.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a write-inhibit circuit for use in asemiconductor integrated circuit including a nonvolatile memory, an inkcartridge 10 including the semiconductor integrated circuit, and anink-jet recording apparatus in which the ink cartridge is mounted.

2. Background Art

Conventionally, in a case in which a power-supply voltage decreases dueto some cause when the desired data is written in a nonvolatile memorybuilt into a semiconductor integrated circuit, miswriting may beperformed. To prevent the miswriting, a write-inhibit circuit may beprovided in the semiconductor integrated circuit.

FIG. 13 is a block diagram showing an example of a write-inhibit circuitbuilt into a semiconductor integrated circuit. In this figure, awrite-inhibit circuit 100 includes a resistor array 101, an operationalamplifier 102, a bias circuit 103, a logic gate 104, and areference-voltage supply 105.

The resistor array 101 is formed by a resistor R1 and a resistor R2which are connected in series. One end of the resistor R1 is connectedto a high-potential power supply VDD. One end of the resistor R2 isconnected to a low-potential power supply VSS. By connecting thejunction of the resistor R1 and the resistor R2 to the gate of atransistor Q2, a voltage that is divided corresponding to a resistanceratio between the resistor R1 and the resistor R2 is applied to the gateof the transistor Q2.

The operational amplifier 102 is formed such that the transistors Q1 andQ2, which are connected in series, are connected in parallel totransistors Q3 and Q4. The gates of the transistors Q1 and Q3 areconnected in common, and are connected to the junction of the transistorQ1 and transistor Q2. The junction of the transistor Q3 and thetransistor Q4 is connected as an output end to the gate of a transistorQ6 at the subsequent stage. A reference voltage Vref is applied from thereference-voltage supply 105 to the gate of the transistor Q4.

The bias circuit 103 is provided between a low-potential connection end(the junction of the transistors Q2 and Q4) of the operational amplifier102 and the low potential power supply VSS, and includes the transistorQ5, which is applied a power-supply voltage Vreg having a predeterminedpotential, and a transistor Q7 connected in common to the back gate ofthe transistor Q5.

The logic gate 104 is formed by a NOR gate G11. The NOR gate G11 has oneinput end to which an inverted signal of a writing request signal WR isinput. Also, the junction of the transistor Q6 and the transistor Q7 isconnected to the other input end of the NOR gate G11, so that thepotential of the junction is input, and an inverted signal of a logicaladdition of the inputs is output.

In the above-described construction, when the voltage value of the highpotential power supply VDD is sufficiently higher than the referencevoltage Vref of the reference-voltage supply 105, the output of theoperational amplifier 102 is at “L”, and the transistor Q6 is inoff-state. Then, “L” is applied to the other input end of the NOR gateG11, so that the data-writing request signal WR is unchanged and outputas a write-control signal WRITE.

In addition, in a case in which the voltage value of the high potentialpower supply VDD decreases for some reason, the voltage applied to thetransistor Q2, which is divided by the resistor array 101, is less thanthe reference voltage Vref, the output of the operational amplifier 102is at “H”, so that the transistor Q6 is in on-state.

At this time, “H” is applied to the other input end of the NOR gate G11.Thus, irrespective of whether the data-writing request signal WR iseither at “H” or “L”, the write-control signal WRITE is at “L”. In otherwords, the power-supply voltage decreases, and miswriting can beprevented because writing by the data-writing request signal WR cannotbe performed.

The write-inhibit circuit 100 has a relatively high detection precisionsince it uses the operational amplifier 102. However, the write-inhibitcircuit 100 has the following defects. Specifically, the write-inhibitcircuit 100 must include, other than the operational amplifier 102, theresistor array 101, the bias circuit 103, the logic gate 104, and thereference-voltage supply 105. Among these, in particular, the resistorarray 101, the logic gate 104, and the reference-voltage supply 105 arelarge in circuit size. Accordingly, provision of these in thesemiconductor integrated circuit causes a drawback in that the chip areaincreases.

In addition, in order that the write-inhibit circuit 100 may operate, itis required that, by using the bias circuit 103, a current always flowin the operational amplifier 102. This causes a defect in that theoperating current increases increasing the power consumption andgenerated heat increases.

The present invention is made to solve the above defects in the relatedart, and an object thereof is to reduce a chip area and to provide awrite-inhibit circuit in which power consumption is reduced, asemiconductor integrated circuit using the same, an ink cartridgeincluding the semiconductor integrated circuit, and an ink-jet recordingapparatus.

Disclosure of Invention

A write-inhibit circuit of the present invention is a write-inhibitcircuit using a data-writing request signal as an input and using anoutput write-control signal to inhibit data writing. The write-inhibitcircuit includes a current mirror circuit in which a first transistorarray that is formed by connecting in series a plurality of transistorsincluding a depletion transistor, used as a reference-current supplybetween a high potential power supply and a low potential power supply,is connected in parallel to a second transistor array that is formed byconnecting a plurality of transistors between the high potential powersupply and the low potential power supply, wherein the write-inhibitcircuit leads an output in accordance with the result of comparisonbetween a reference current from the reference-current supply and acurrent in accordance with the input signal, and when the voltage of thehigh potential power supply decreases, the write-inhibit circuit leadsan output in accordance with the reference current from thereference-current supply.

The second transistor array is formed by connecting in series a firsttransistor which is connected to the high potential power supply andwhich is switched on in accordance with the data-writing request signal,a second transistor which allows a current equal to that flowing via thefirst transistor to flow in the first transistor array, and a thirdtransistor which is switched on together with the first transistor andwhich forms a current path to the low potential power supply; the firsttransistor array is formed by connecting in series a fourth transistorwhich is connected to the high potential power supply and which isswitched on in accordance with the data-writing request signal, a fifthtransistor having a gate electrode connected in common to the gateterminal of the second transistor, and a sixth transistor as thedepletion transistor; and the write-control signal is output from thejunction of the fifth transistor and the sixth transistor.

A semiconductor integrated circuit of the present invention includes:the above write-inhibit circuit; a memory cell for storing data at adesignated address; and an address generating circuit for sequentiallygenerating addresses for designation in the memory cell. The writing ofthe data in the memory cell is inhibited based on a write-control signaloutput from the write-inhibit circuit.

The semiconductor integrated circuit further includes a control meansfor performing control so as to perform transfer to a low powerconsumption mode having power consumption less than a normal operatingmode for performing a normal operation. The semiconductor integratedcircuit may be provided in an ink cartridge, and may perform transfer tothe low power consumption mode in response to the termination of aprinting operation using the ink cartridge. The address may beinitialized when the control means performs transfer to the low powerconsumption mode.

In the low power consumption mode activated by the control means, theoperations of internal circuits are terminated, such as a senseamplifier for generating a signal for reading data stored in the storagemeans, an address decoder for designating an address in the storagemeans, a buffer used when data read from the storage means is read, anda latch circuit for latching data read from the storage means.

The transfer to the low power consumption mode, and the initializationof the address generated by the address generating means may beperformed based on a control signal input to a common external terminal.The common external terminal is, for example, a chip-select terminal.

An ink cartridge of the present invention includes the abovesemiconductor integrated circuit, and stores at least the remainingamount of ink.

An ink-jet recording apparatus of the present invention has the aboveink cartridge, and uses ink supplied from the ink cartridge to print thedesired image information.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an example of a write-inhibitcircuit according to an embodiment of the present invention.

FIG. 2 is a functional block diagram illustrating the internal structureof a semiconductor integrated circuit including the write-inhibitcircuit in FIG. 1.

FIG. 3 is a functional block diagram illustrating the internal structureof another semiconductor integrated circuit.

FIG. 4 is a circuit digital showing an example of a write-inhibitcircuit used in the semiconductor integrated circuit in FIG. 3.

FIG. 5 is a timing chart illustrating the operation of reading withrespect to a semiconductor integrated circuit.

FIG. 6 is a timing chart illustrating a writing operation, etc., from asemiconductor integrated circuit.

FIG. 7 is a drawing showing a circuit board on which the semiconductorintegrated circuit shown in the embodiment is mounted.

FIG. 8 is a drawing showing that the circuit board shown in FIG. 7 ismounted in an ink cartridge.

FIG. 9 is an illustration of an ink-jet printer in which the inkcartridge shown in FIG. 8 is mounted.

FIG. 10 is an illustration of the structure of the carriage shown inFIG. 9.

FIG. 11 is an illustration of a state before an ink cartridge is mountedin a holder.

FIG. 12 is a drawing showing that an ink cartridge is mounted in aholder.

FIG. 13 is a block diagram showing an example of a conventionalwrite-inhibit circuit.

BEST MODE FOR CARRYING OUT THE INVENTION

Next, an embodiment of the present invention is described with referenceto the drawings. In each drawing to be referred in the followingdescription, portions identical to those in other drawings are denotedby identical reference numerals.

FIG. 1 is a showing a write-inhibit circuit according to the embodiment.In this figure, a write-inhibit circuit 10 includes a buffer gate B1, acurrent-mirror circuit CM, and a buffer gate B2. The current-mirrorcircuit CM includes a first transistor array of transistors T1 to T3,and a second transistor array of transistors T4 to T6.

Here, the transistors T1 to T5 are enhancement transistors in which, byapplying a voltage not less than a threshold value across the gate andthe source of each transistor, a channel is formed across the source andthe drain of each transistor, causing current flow. The transistor T6 isa depletion transistor in which a current flows across a source and adrain even if a gate voltage is zero.

The buffer gate B1 uses a write-request signal WR as an input, andoutputs a signal obtained by inverting and amplifying the input. Theoutput end of the buffer gate B1 is connected to the gate of thetransistor T1. The buffer gate B2 inverts and amplifies an output fromthe current mirror circuit, and outputs the obtained signal as awrite-control signal.

The current-mirror circuit CM is formed such that between a highpotential power supply VDD and a low potential power supply VSS, a firsttransistor array formed by connecting in series a P-channel MOStransistor (hereinafter referred to as a P-transistor) T1, aP-transistor T2, and an N-channel MOS transistor (hereinafter referredto as an N-transistor) T3 in this order is connected in parallel to asecond transistor array formed by a P-transistor T4, a P-transistor T5,and an N-transistor T6 in this order.

The P transistor T1 has a gate connected to the output end of the buffergate B1. The gate of the transistor T1 is also connected to the gate ofthe P-transistor T4. The P-transistor T2 has a gate connected to thegate of the gate of the P-transistor T5, and the connection end is alsoconnected to a junction to the N-transistor T3.

The N-transistor T3 is connected to a signal line to which thewrite-request signal WR is input. A junction of the P-transistor T5 andthe N-transistor T6 is used as an output end of the current-mirrorcircuit CM, and the output end is connected to the input end of thebuffer gate B2. A low potential voltage having a predetermined potentialis applied to the gate of the N-transistor T6 so that a referencecurrent Iref flows in the N-transistor T6. In this case, by forming theN-transistor T6 to be of a depletion type, the reference current Irefcan flow also in a normal state.

As described above, this write-inhibit circuit is a write-inhibitcircuit to which the signal WR for requesting data writing is input andthat inhibits data writing by using a write-control signal WRITE to beoutput. This write-inhibit circuit includes the current-mirror circuitCM formed such that a first transistor array in which a plurality oftransistors including a depletion transistor for use in a referencecurrent supply are connected in series between the high potential powersupply VDD and the low potential power supply VSS is connected inparallel to a second array of transistors that are connected in seriesbetween the high potential power supply VDD and the low potential powersupply VSS and that allows a current in accordance with the data-writingrequest signal WR to flow. The current-mirror circuit CM operates so asto lead an output (the write-control signal WRITE) in accordance withthe result of comparing the reference current Iref and an input signaland so as to lead an output in accordance with the reference currentIref when the voltage of the high potential power supply decreases.

The first transistor array is formed by connecting in series thetransistor T1, which is connected to the high potential power supply VDDand which is switched on in accordance with the data-writing requestsignal WR, the transistor T2, which allows a current equal to a currentflowing via the transistor T1 to flow in the first transistor array, andthe transistor T3, which is switched on simultaneously with thetransistor T2 so that a current path to the low potential power supplyVSS is formed. Also, the second transistor array is formed by connectingin series the transistor T4, which is connected to the high potentialpower supply VDD and which is switched on in accordance with thedata-writing request signal WR, the transistor T5, which has a gateelectrode connected in common to the gate electrode of the transistorT2, and the transistor T6 as a depletion transistor. From a junction ofthe transistor T5 and the transistor T6, the write-control signal WRITEis output through buffer B2.

In the above-described construction, the current-mirror circuit CM candetect the voltage value of the high potential power supply VDD bycomparing the reference current Iref and a current ID flowing across thesource and drain of the N-transistor T3. In other words, when thevoltage value of the high potential power supply VDD is sufficientlyhigh, the data-writing request signal WR is directly output as awrite-control signal. In other words, when the data-writing requestsignal WR is “L”, the write-control signal is “L”, and when thedata-writing request signal WR is “H”, the write-control signal is “H”.

In addition, if the voltage value of the high potential power supply VDDdecreases due to some reason, the transistor T6 for use in the referencecurrent supply and the buffer gate B2 cause the write-control signal tobe “L” irrespective of whether the data-writing request signal WR is “H”or “L”. In other words, when the power supply voltage decreases, writingby the data-writing request signal WR cannot be performed, so thatmiswriting can be prevented.

In other words, the circuit compares a voltage current to be measuredand a reference current, performs voltage detection based on thedifference current, and inhibits data writing when the detected voltagevalue is a predetermined voltage value or less. The transistorsconstituting the circuit are all MOS transistors, and it is clear thatthey can be easily formed by an ordinary semiconductor productionprocess.

The above basis operation is similar to that in FIG. 13. However, inthis embodiment, by using the current-mirror circuit CM to compare thereference current Iref by the reference current supply and the currentID, voltage-detection and write-inhibit circuits can be integrated, sothat the circuit size can be reduced. Also, since no operationalamplifier and no voltage-dividing resistor are used, the currentconsumption can be suppressed, and heat generation can be suppressed.

FIG. 2 is a functional block diagram illustrating the internal structureof a semiconductor integrated circuit using the above-describedwrite-inhibit circuit in FIG. 1.

As shown in the figure, a semiconductor integrated circuit 1 includes anaddress counter 2 for performing a counting operation, a row decoder 3and a column decoder 4 which each generate an address by decoding thecount value from the address counter 2, a memory-cell array 5 forstoring data, a write/read control circuit 6 that controls a latchcircuit 7 in accordance with writing to or reading from the memory-cellarray 5, the latch circuit 7, which is controlled to be in latch-stateor through-state by the write/read control circuit 6, an input/outputcontrol circuit 8 that controls data input/output with respect to thememory-cell array 5, AND gates G1 to G3, and a write-inhibit circuit 10.The semiconductor integrated circuit 1 is provided with externalterminals P1 to P6.

In the address counter 2, the count value is initialized (reset) to apredetermined value, based on an inverted signal of a chip-select inputsignal CS input from the external terminal P1. The address counter 2also generates address data updated based on a signal input from the ANDgate G1. The generated address data is input to the row decoder 3 andthe column decoder 4.

The column decoder 4 selects the desired column of memory cells in thememory-cell array 5 based on the address data input from the addresscounter 2. Similarly, the row decoder 3 selects the desired row ofmemory cells in the memory-cell array 5 based on the address data inputfrom the address counter 2.

The memory-cell array 5 is formed by arranging a plurality of memorycells in the form of a grid. Each memory cell is switched on by aselection signal from the row decoder 3, and is set by a selectionsignal from the column decoder 4 so that reading of information storedin the memory cell and writing can be performed. The memory-cell array 5consists of nonvolatile memory cells.

The write/read control circuit 6 is explained with reference to FIG. 3,and it determines, based on the chip-select signal CS input from theexternal terminal P1 and signals output from the AND gates G2 and G3,the operation of either writing to, or reading from, the memory-cellarray 5. The write/read control circuit 6 outputs a control signal tothe latch circuit 7 via the AND gate G4. A standby signal STB5 is inputto either of the inputs of the AND gate G4. Accordingly, when thestandby signal STB5 is in low level, the output of the AND gate G4 is inlow level, and when it is in high level, the output of the AND gate G4is equivalent to an output signal from the write/read control circuit 6.

Returning to FIG. 2, based on a control signal from the write/readcontrol circuit 6, the latch circuit 7 outputs data read from thememory-cell array 5, which is output from the input/output controlcircuit 8, after holding the data for a predetermined time. The latchcircuit 7 performs either a latch operation or a through operation inaccordance with the output of the write/read control circuit 6. When theoutput of the write/read control circuit 6 is in low level, the latchcircuit 7 performs the latch operation, and when the output of thewrite/read control circuit 6 is in high level, the latch circuit 7performs the through-operation. The latch operation is an operation thatmaintains an output state. The through-operation is an operation thatdirectly sends an input signal as an output signal.

The input/output control circuit 8 writes data input from the externalterminal P6 to the memory-cell array 5, and, in reverse, outputs dataread from the memory-cell array 5 to the external terminal P6 via thelatch circuit 7.

The AND gate G1 outputs, to the address counter 2 and the AND gates G2and G3, a signal as a logical multiplication of the chip-select controlsignal CS input from the external terminal P1 and a clock input signalCK input from the external terminal P2.

The AND gate G2 outputs a signal as a logical multiplication of anoutput signal from the AND gate G1 and a write/read input signal W/Rfrom the external terminal P3. This signal is the above data-writingrequest signal WR. The data-writing request signal WR is input to thewrite/read control circuit 6. The data-writing request signal WR is alsoinput as a write-control signal to the input/output control circuit 8via the write-inhibit circuit 10. In addition, the AND gate G3 outputs,to the write/read control circuit 6, a signal as a logicalmultiplication of the output signal from the AND gate G1 and an invertedsignal of the write/read input signal W/R.

Specifically, when the input signal from the AND gate G1 is “L”, theoutputs of the AND gates G2 and G3 are both “L”. Also, when the inputsignal from the AND gate G1 is “H”, if the write/read input signal W/Ris “H”, the output of the AND gate G3 is “L”. Conversely, when thewrite/read input signal W/R is “L”, the output of the AND gate G2 is“L”, so that the output of the AND gate G3 is “H”. As described, the ANDgates G2 and G3 are designed so that their outputs are not unstable evenif the write/read input signal W/R changes.

The external terminal P1 is a terminal for inputting the chip-selectsignal CS as a control signal for selecting a particular device when aplurality of devices exist simultaneously, for initialization of theaddress counter 2, and for transfer of the operating mode. In otherwords, the external terminal P1 in this embodiment is a terminal usedboth as a control terminal for address-counter initialization and as anoperating-mode control terminal.

The external terminal P2 is a terminal for inputting the clock signalCK, which is a reference used when the semiconductor integrated circuit1 operates. The external terminal P3 is a terminal for inputting thewrite/read input signal W/R, which designates the operation of accessingthe memory-cell array 5 built into the semiconductor integrated circuit1.

The external terminals P4 and P5 are input terminals for applying theoperating voltages of the high potential power supply VDD and the lowpotential power supply VSS for the operation of the semiconductorintegrated circuit 1. The external terminal P6 is an input/outputterminal for inputting data to be actually written into the memory-cellarray 5 built into the semiconductor integrated circuit 1 and foroutputting data read from the memory-cell array 5.

In the above-described construction, when the voltage level of the highpotential power supply VDD is normal, write inhibition by thewrite-inhibit circuit is not performed, as described above. Accordingly,in this case, the data-writing request signal WR is unchanged and outputas the write-control signal WRITE, and writing of predetermined data isperformed.

Conversely, when the voltage level of the high potential power supplyVDD decreases, the write-control signal WRITE can be set to be at “L”irrespective of whether the data-writing request signal WR is at “H” or“L”. This can inhibit miswriting.

In order to reduce the power consumption, the semiconductor integratedcircuit 1 shown in FIG. 3 may be employed. In the semiconductorintegrated circuit 1 shown in this figure, AND gates, etc., are added,and a reduction in the power consumption is achieved by terminating theoperation of the internal circuit in accordance with their outputs. Inthis figure, the semiconductor integrated circuit 1 is obtained byadding, to the structure of FIG. 2, AND gates G4 to G7, a buffer Bcontrolled to be in enable state or high impedance (Hi-Z) state by thewrite/read control circuit 6, a voltage-detection circuit 9, and aninverter INV.

The output lines of the row decoder 3 are provided with the AND gatesG6, respectively, and a standby signal STB4 is input to either of theinputs of each AND gate G6. Thus, when the standby signal STB4 is in lowlevel, no row of memory cells in the memory-cell array 5 is selected.

The write/read control circuit 6 outputs a control signal to a latchcircuit 7 via the AND gate G4. A standby signal STB5 is input to eitherof the inputs of the AND gate G4. Accordingly, when the standby signalSTB5 is in low level, the output of the AND gate G4 is in low level, andwhen it is in high level, the output of the AND gate G4 is equivalent tothe output signal of the write/read control circuit 6.

The latch circuit 7 performs either of a latch operation and a throughoperation in accordance with the output of the AND gate G4. When theoutput of the AND gate G4 is in low level, the latch circuit 7 performsthe latch operation, and when the output of the AND gate G4 is in highlevel, the latch circuit 7 performs the through-operation.

The buffer B is provided between the output of the latch circuit 7 andthe external terminal P6. The buffer B is in enable state or highimpedance state in accordance with an output from the AND gate G5 towhich the standby signal STB3 and a control signal from the write/readcontrol circuit 6 are input. When the standby signal STB3 as an outputis in low level, the output of the AND gate G5 is in low level, and whenit is in high level, the output of the AND gate G5 is equivalent to theoutput signal of the write/read control circuit 6. When the output ofthe AND gate G5 is in high level, and the buffer B is in enable state,the output of the latch circuit 7 is lead from the external terminal P6.Conversely, when the buffer B is in high impedance state, a signal givento the external terminal P6 is input to the input/output control circuit8.

The input/output control circuit 8 includes a sense amplifier 81 that isoperated by the standby signal STB2, and a write circuit 9 that performswriting to a memory-cell array 5 in accordance with an output from thewrite-inhibit circuit and an input/output signal I/O.

The write-inhibit circuit 10 has a function of controlling the writecircuit 9 in the input/output control circuit 8 in accordance with thevoltage levels of the data-writing request signal WR and the standbysignal STB1. In a case in which this semiconductor integrated circuit isprovided in an ink cartridge, data written in the memory-cell array 5is, for example, the remaining amount of ink. By writing the remainingamount of ink, the remaining amount of ink can be always monitored.

The above standby signals STB1 to STB5 are generated by the AND gate G7and the inverter INV. The standby signal STB1 is generated by the ANDgate G7, which outputs a logical multiplication of the standby signalSTB0 and the write/read input signal W/R. The standby signals STB2,STB3, and STB5 are generated by the inverter INV, which outputs aninverted signal of the write/read input signal W/R. The standby signalSTBO is unchanged and used as the standby signal STB4.

In the semiconductor integrated circuit shown in FIG. 3, the internalstructure of the write-inhibit circuit 10 can be changed to that shownin FIG. 4. Referring to this figure, instead of inputting thedata-writing request signal WR to the buffer gate B1, the standby signalSTB1 is input to the buffer gate B1. Also in this structure, similarlyto the case in the above FIG. 1, when the voltage level of the highpotential power supply decreases, the write-control signal WRITE can beat “L” irrespective of whether the data-writing request signal WR iseither “H” or “L”. The can inhibit miswriting.

Next, the operation of the semiconductor integrated circuit shown inFIG. 3 is described with reference to FIG. 5 and FIG. 6.

FIG. 5 is a timing chart illustrating the operation of reading on thesemiconductor integrated circuit. This figure shows the chip-selectsignal CS, the write/read input signal W/R, the clock CLOCK, the countvalue by the address counter 2, and the input/output signal I/O at theexternal terminal P6, which are in FIG. 1. When reading on thememory-cell array 5 is performed, by initially applying “L” to theexternal terminal P1, the address counter 2 is initialized. Next, “H” isapplied to the external terminal P1, and clock pulses for a targetedread-start address are input from the external terminal P2. While theclock pulses are being input, “L” that designates reading is input asthe write/read input signal W/R from the external terminal P3.

Data corresponding to the address is output in a period in which theclock signal CK is at “L”, and is output from the external terminal P6.Since the data is latched in the latch circuit 7 in the rise of theclock pulses, its value is held in a period in which the clock signal CKis at “H”. After the clock pulses rise, the address is incremented, anddata at the next address is output from the external terminal P6.

FIG. 6 is a timing chart illustrating a writing operation, etc., fromthe semiconductor integrated circuit. This figure shows the standbysignals STB1 to STB5 in addition to the chip-select signal CS, thewrite/read input signal W/R, the clock CLOCK, the count value by theaddress counter 2, and the input/output signal I/O at the externalterminal P6. When writing to the memory-cell array 5 is performed, in aread mode, that is, a state in which the write/read input signal W/R isat “L”, by initially applying “L” to the external terminal P1, theaddress counter 2 is initialized. Next, “H” is applied to the externalterminal P1, and clock pulses for a targeted write-start address areinput from the external terminal P2. After that, during the operation ofwriting, “H” that designates writing is applied as the write/read inputsignal W/R from the external terminal P3.

Next, a process in a case in which memory initialization and operatingmode transfer are instructed is described. As described above, theapplication of “L” to the external terminal P1 initializes the addresscounter 2. This is an absolute required procedure for initializing thesemiconductor integrated circuit, and is similar in the case of thewrite/read control circuit 6, etc., other than the memory-cell array 5.At this time, the output of the buffer B is in the Hi-Z state, and theexternal terminal P6 is open (in a high impedance state).

When printing by an ink-jet recording apparatus ends, “L” is input tothe external terminal P1. This causes the standby signal STBO foroperating mode transfer to be at “L”, so that the operating mode of thesemiconductor integrated circuit 1 is in a standby mode. When theoperating mode of the semiconductor integrated circuit 1 is in thestandby mode, a portion in which a current constantly flows isterminated so that reduction in the current consumption is achieved.Specifically, for example, it is common that the sense amplifier 81provided in the input/output control circuit 8 is formed by a currentmirror circuit. It is required that a current constantly flow in thesense amplifier 81. Accordingly, to reduce the current consumption, inthe case of the standby mode, the standby signal STB2 is used to switchoff a power-supply voltage supplied to the input/output control circuit8. Similarly, the standby signal STBL is used to switch off thevoltage-detection circuit 9, which is formed by a current mirrorcircuit.

In addition, the standby signal STB3 is used to set the buffer B asanother internal circuit to be in high impedance state. The latchcircuit 7 is controlled to be in latched state by the standby signalSTB5. Address designation by the row decoder 3 is deterred by thestandby signal STB4.

As described, in this embodiment, when the chip-select signal CS is at“L”, that is, in a case in which the external terminal P1 is in anon-selected state, the address counter 2 is initialized and thesemiconductor integrated circuit is in standby mode. These instructionsare controlled by an input from the external terminal P1, which is usedfor another purpose, whereby reduction of external terminal reductioncan be achieved while this embodiment has the memory initializationfunction and the function of transferring to the standby mode. Becausethe memory initialization control terminal and the operating modecontrol terminal are integrated into a common terminal, control thereofis also simplified.

The circuit block initialization and operating mode transfer functionsmay be modified such that, when a logical output of an input from theexternal terminal P1 and an input from another terminal is innon-selected state, the address counter 2 is initialized and thesemiconductor integrated circuit 1 enters the standby mode.

In FIG. 7, (a) to (e) are illustrations of a circuit board on which asemiconductor integrated circuit according to this embodiment ismounted. As shown in (a) of this figure, a circuit board 11 has contactsformed on the surface thereof. These contacts 12 are connected to theabove external terminals P1 to P6. Also, as shown in (b) of this figure,on the back surface of the circuit board 11, a semiconductor integratedcircuit 1 is mounted.

As shown in (c) of this figure, the circuit board 11 has anapproximately rectangular plate shape. The circuit board 11 is providedwith a cut 11 a and a hole 11 b. These are used to determine theposition of the circuit board 11 when it is mounted on an ink cartridgewhich is described later. As shown in (d) of this figure, on thesurfaces of the contacts 12 provided on the circuit board 11, concaveportions 12 a may be provided. By providing the concave portions 12 a,the state of electric connection to a contact 29 provided in the inkcartridge which is described later can be made preferable, as shown in(e) of this figure.

In FIG. 8, (a) and (b) are illustrations of the circuit board shown inFIG. 7 when it is mounted on the ink cartridge. In this figure, (a)shows that the circuit board 11 is mounted on a black ink cartridge 20containing black ink. The black ink cartridge 20 contains ablack-ink-impregnated porous material (not shown) in a container 21formed almost as a rectangular parallelepiped, and its top surface issealed by a cover member 23. On the bottom of the container 21, anink-supply outlet 24 is formed at a position opposing an ink-supplyneedle when the container 21 is mounted on a holder. At the top end of avertical wall 25 on the ink-supply outlet side, extended portions 26that are engaged in a projection of a lever on the main unit side areformed in an incorporated form. The extended portions 26 are separatelyformed on both sides of the wall 25, and has a rib 26 a. Between a lowerarea and the wall 25, a triangular rib 27 is formed.

On the ink-supply-outlet-formed side, the circuit board 11 is formed.The circuit board 11 has a plurality of contacts on a surface opposingcontacts of the main unit, and a storage device mounted on the back ofthe surface. On the vertical wall 25, projections 25 a and 25 b, andextended portions 25 c and 25 d for determining the position of thecircuit board 11 are formed.

In this figure, (b) shows that the mounted circuit board 11 is mountedin a color-ink cartridge 30 containing color ink. The color-inkcartridge 30 contains an ink-impregnated porous material in a container31 formed almost as a rectangular parallelepiped, and its top surface issealed by a cover member 31. Inside the container 51, five inkcontainers for separately containing five color inks are separatelyformed. On the bottom of the container 31, ink-supply outlets 34corresponding to the ink colors are formed at positions opposingink-supply needles. At the top end of a vertical wall 35, extendedportions 36 that are engaged in lever projections of the main unit sideare formed in an incorporated form. The extended portions 36 areseparately formed on both sides of the wall 35, and have ribs 36 a.Between a lower area and the wall 35, triangular ribs 37 are formed.Also, the container 35 has a concave portion 39 for preventingmis-insertion.

On the ink-supply-outlet-formed side on the vertical wall 35, a concaveportion 38 is formed so as to be positioned in the center of thelongitudinal direction of the cartridge 30, and the circuit board 11 ismounted thereon. The circuit board 11 has a plurality of contacts on asurface opposing contacts of the main unit, and on its back, a storagedevice is mounted. On the vertical wall 35, projections 35 a and 35 band extended portions 35 c and 35 d for determining the position of thecircuit board 11 are formed.

FIG. 9 is an illustration of the overview of an ink-jet printer (ink-jetrecording apparatus) in which the ink cartridge shown in FIG. 8 ismounted. In this figure, in a carriage 43 connected to a driving motor42 via a timing belt 41, a holder 44 is formed which contains the blackink cartridge 20 shown in (a) of FIG. 8, and the color-ink cartridge 30shown in (b) of FIG. 8. Below the carriage 43, a recording head 45 towhich ink is supplied from the each of the ink cartridges 20 and 30.

Ink-supply needles 46 and 47 that are linked to the recording head 45are vertically provided on the bottom of the carriage 43 so as to bepositioned in the back of the unit, that is, on the side of the timingbelt 41.

FIG. 10 is an illustration of the structure of the carriage shown inFIG. 9. As shown in this figure, among vertical walls forming the holder44, at the top end of a vertical wall 48 opposing the vicinities of theink-supply needles 46 and 46, levers 51 and 52 are provided usingspindles 49 and 50 as fulcrums so as to rotate.

A wall 53, positioned on the free-end side of the levers 51 and 52, hasan inclined surface portion. The vertical wall 48 is provided withcontact mechanisms 54 and 55. The contact mechanisms 54 and 55 areelectrically connected to the contacts provided on the above circuitboard 11 when the cartridge is mounted. This makes it possible to usethe ink in each ink cartridge to perform ink-jet recording.

A base 56 is provided to the vertical wall 48 of the holder 44. On theback of the base 56, a circuit board 57 is provided. Since the circuitboard 57 is electrically connected to the contact mechanisms 54 and 55,the circuit board 11 and the circuit board 57, which are provided in theink cartridge, are electrically connected to each other.

FIG. 11 is an illustration of a state obtained before mounting the inkcartridge in the holder, and in FIG. 12, (a) to (c) are illustrationsshowing that the ink cartridge is mounted in the holder. As shown inFIG. 11, when the lever 51 is lclosed while the ink cartridge 20 ismounted in the holder 44, the ink cartridge 20 is gradually lowered inthe direction of the arrow Y. At this time, as the state shown in (a) ofFIG. 12 transfers to the state shown in (c) of FIG. 12, the ink-supplyneedle 46 is inserted into the ink cartridge 20. When the ink-supplyneedle 46 is inserted into the ink cartridge 20, and the ink cartridge20 is completely mounted in the holder 44, that is, in the state shownin (c) of FIG. 12, ink is supplied from the ink cartridge 20.

In the state shown in (c) of FIG. 12, the contact 12 provided on thecircuit board 11, and the contact 29 on the circuit board 56 provided onthe side of the holder 44 are electrically connected to each other. Thisenables the ink-jet printer to freely performing data reading/writingwith respect to the semiconductor integrated circuit 1. Specifically,when the power supply of the printer is switched on, “L” is applied tothe external terminal P1, and when the reading/writing operation isperformed, “H” is applied. This can simplify logic, and can contributeto a reduction in the chip size.

Industrial Applicability

As described above, by using the write-inhibit circuit according to theembodiment, the circuit size can be reduced and the power consumptioncan be reduced, although the precision of detection is inferior to acase using an operational amplifier, whereby the write-inhibit circuitis the most suitable for provision to mass-produced products such as inkcartridges.

By using a semiconductor integrated circuit including the write-inhibitcircuit in a ink cartridge, and performing control so that transfer to alow power consumption mode is performed in response to the terminationof printing operation using the ink cartridge, the operating mode can betransferred without affecting the normal operation. In the low powerconsumption mode, by initializing a designated address, reduction in thepower consumption can be achieved. Also, in the low power consumptionmode, by terminating the operations of internal circuits such as a senseamplifier for generating a signal for reading stored data, an addressdecoder for designating an address, a buffer used when the read data isread, and a latch circuit for latching the read data, the powerconsumption can be further reduced.

In addition, by using, in common, terminals for instructing acircuit-block initializing function and the function of transferring tothe standby mode, an external-terminal-reduced semiconductor integratedcircuit is realized.

Moreover, by storing at least the remaining amount of ink in the inkcartridge, the remaining amount of ink can be always monitored.

What is claimed is:
 1. A write-inhibit circuit comprising: an input nodefor receiving a data-writing request signal; an output node foroutputting an output write-control signal to inhibit data writing; acurrent mirror circuit having a first transistor array in parallel witha second transistor array between a high potential power supply and alow potential power supply, said first transistor array including afirst plurality of series-connected transistors including a depletiontransistor for generating a reference-current, said second transistorarray including a second plurality of transistors and being effectivefor producing a signal current in response to the data-writing requestsignal received at said input node; wherein the write-inhibit circuit iseffective for providing an output signal at said output node indicativeof a comparison between said reference current and said signal currentwhen the voltage of said high potential power supply is not lower than apredetermined value, and when the voltage of said high potential powersupply decreases below said predetermine value, the write-inhibitcircuit is effective for providing a second output signal at said outputnode determined only by said reference current.
 2. A write-inhibitcircuit as set forth in claim 1, wherein: the second transistor array isformed by connecting in series a first transistor which is connected tothe high potential power supply and which is switched on in accordancewith the data-writing request signal, a second transistor which allows acurrent equal to that flowing via the first transistor to flow in thefirst transistor array, and a third transistor which is switched ontogether with the first transistor and which forms a current path to thelow potential power supply; the first transistor array is formed byconnecting in series a fourth transistor which is connected to the highpotential power supply and which is switched on in accordance with thedata-writing request signal, a fifth transistor having a gate electrodeconnected in common to the gate terminal of the second transistor, and asixth transistor as the depletion transistor; and the write-controlsignal is output from the junction of the fifth transistor and the sixthtransistor.
 3. A semiconductor integrated circuit including: awrite-inhibit circuit as set forth in claim 1; a memory store of memorycells for storing data at a designated address; and an addressgenerating circuit for sequentially generating addresses for designationin the memory store; wherein the writing of the data in the memory storeis inhibited based on said write-control signal output from thewrite-inhibit circuit.
 4. A semiconductor integrated circuit as setforth in claim 3, further including control means for performing controlso as to perform transfer to a low power consumption mode having powerconsumption less than a normal operating mode for performing a normaloperation, wherein the semiconductor integrated circuit is provided inan ink cartridge, and performs transfer to the low power consumptionmode in response to the termination of a printing operation using theink cartridge.
 5. A semiconductor integrated circuit as set forth inclaim 4, wherein the address is initialized when the control meansperforms transfer to the low power consumption mode.
 6. A semiconductorintegrated circuit as set forth in claim 5, wherein in the low powerconsumption mode activated by the control means, the operation of aninternal circuit is terminated.
 7. A semiconductor integrated circuit asset forth in claim 6, wherein the internal circuit is a sense amplifierfor generating a signal in response to reading data stored in the memorystore.
 8. A semiconductor integrated circuit as set forth in claim 6,wherein the internal circuit is an address decoder for designating anaddress in the memory store.
 9. A semiconductor integrated circuit asset forth in claim 6, wherein the internal circuit is a buffer used whendata is read from the memory store.
 10. A semiconductor integratedcircuit as set forth in claim 6, wherein the internal circuit is a latchcircuit for latching data read from the memory store.
 11. Asemiconductor integrated circuit as set forth in claim 4, whereinimplementation of the transfer to the low power consumption mode and theinitialization of the address generated by the address generatingcircuit is based on a control signal input to a common externalterminal.
 12. A semiconductor integrated circuit as set forth in claim11, wherein the common external terminal is a chip-select terminal. 13.An ink cartridge including a semiconductor integrated circuit as setforth in claim 3, wherein a value of the remaining amount of ink in saidink cartridge is stored in said memory store.
 14. An ink-jet recordingapparatus having an ink cartridge as set forth in claim 13, wherein theink-jet recording apparatus uses ink supplied from the ink cartridge toprint image information.